Modern network processors (NPs) typically resemble a highly-multithreaded multiprocessor-on- a-chip, supporting a wide variety of mechanisms for on-chip storage and inter-task communication. NP applications are themselves composed of many threads that share memory and other resources, and synchronize and communicate frequently. In contrast, studies of new NP architectures and fea- tures are often performed by benchmarking a simulation model of the new NP using independent kernel programs that neither communicate nor share memory. In this paper we present a NP sim- ulation infrastructure that (i) uses realistic NP applications that are multithreaded, share memory, synchronize, and communicate; and (ii) automatically maps these applications to a variety of NP architectures and features. We use our infrastructure to evaluate threading and scaling, on-chip storage and communication, and to suggest future techniques for automated compilation for NPs.
"Towards a Compilation Infrastructure for Network Processors"
Martin Labrecque
Masters Thesis, Department of Electrical and Computer Engineering, University of Toronto, January, 2006.
@MASTERSTHESIS{np_thesis06,
author = {Martin Labrecque},
title = {Towards a Compilation Infrastructure for Network Processors},
school = {University of Toronto},
year = {2006},
}