A characterization of instruction-level error derating and its implications for error detection
Jeffrey J. Cook and Craig Zilles
Abstract:
Instruction-level derating encompasses the mechanisms by which computation on incorrect values can result in correct computation. We characterize the instruction-level derating that occurs in the SPEC CPU2000 INT benchmarks, classifying it (by source) into six categories: value comparison, sub-word operations, logical operations, overflow/precision, lucky loads, and dynamically-dead values. We also characterize the temporal nature of this derating, demonstrating that the effects of a fault persist in architectural state long after the last time they are referenced. Finally, we demonstrate how this characterization can be used to avoid unnecessary error recoveries (when a fault will be masked by software anyway) in the context of a dual modular redundant (DMR) architecture.
Published:
"A characterization of instruction-level error derating and its implications for error detection"
Jeffrey J. Cook and Craig Zilles.
IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN'08)
, June 2008.
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