Memory subsystem simulation in software TLM/T models
Eric Cheung, Harry Hsieh, and Felice Balarin
Abstract:
Design of Multiprocessor System-on-a-Chips requires efficient and accurate simulation of every component. Since the memory subsystem accounts for up to 50% of the performance and energy expenditures, it has to be considered in system-level design space exploration. In this paper, we present a novel technique to simulate memory accesses in software TLM/T models. We use a compiler to automatically expose all memory accesses in software and annotate them onto efficient TLM/T models. A reverse address map provides target memory addresses for accurate cache and memory simulation. Simulating at more than 10MHz, our models allow realistic architectural design space explorations on memory subsystems. We demonstrate our approach with a design exploration case study of an industrial-strength MPEG-2 decoder.
Published:
"Memory subsystem simulation in software TLM/T models"
Eric Cheung, Harry Hsieh, and Felice Balarin
Proceedings of the 14th Asia South Pacific Design Automation Conference (ASP-DAC'09), Yokohama, Japan, January 09
Bibtex:
@inproceedings{1509814,
author = {Cheung, Eric and Hsieh, Harry and Balarin, Felice},
title = {Memory subsystem simulation in software TLM/T models},
booktitle = {ASP-DAC '09: Proceedings of the 2009 Conference on Asia and South Pacific Design Automation},
year = {2009},
isbn = {978-1-4244-2748-2},
pages = {811--816},
location = {Yokohama, Japan},
publisher = {IEEE Press},
address = {Piscataway, NJ, USA},
}
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